-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Thu Sep  4 04:02:00 2025
-- Host        : localhost.localdomain running 64-bit CentOS Linux release 7.7.1908 (Core)
-- Command     : write_vhdl -force -mode synth_stub
--               /root/work/project/main_pro/main_pro.srcs/sources_1/ip/clk_1/clk_1_stub.vhdl
-- Design      : clk_1
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xczu2eg-sfvc784-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk_1 is
  Port ( 
    clk_o125m : out STD_LOGIC;
    clk_o750m : out STD_LOGIC;
    clk_o250m : out STD_LOGIC;
    clk_o400m : out STD_LOGIC;
    reset : in STD_LOGIC;
    locked : out STD_LOGIC;
    clk_in1_p : in STD_LOGIC;
    clk_in1_n : in STD_LOGIC
  );

end clk_1;

architecture stub of clk_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_o125m,clk_o750m,clk_o250m,clk_o400m,reset,locked,clk_in1_p,clk_in1_n";
begin
end;
